View OV7451_163771.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

www..com
Omni
ision(R)
Applications
* * * * * * *
Advanced Information Preliminary Datasheet
OV7950/OV7451 CMOS Analog NTSC CAMERACHIPTM with OmniPixel(R) Technology General Description
The OV7950 (color) and OV7451 (black & white) single chip CMOS CAMERACHIPSTM are designed to provide a high level of functionality for all applications requiring a small footprint, low voltage, low power consumption and high performance color or B&W video camera. Both devices support NTSC composite video output and can directly interface with a VCR TV monitor or other device with 75 ohm loading.
Security/Surveillance cameras Video Conferencing Video phones Video e-mail Toys Finger print equipment Medical and dental equipment
Key Specifications
Array Size Analog/ADC/IO Power Supply Digital Core Power Consumption Image Area OV7950 Exposure Time Range OV7451 Optical Format S/N Ratio Dynamic Range Pixel Size Dark Current Fixed Pattern Noise Package Dimensions 656 x 492 3.3 VDC + 5% 1.8 VDC + 5% 200 mW 4.080 mm x 3.102 mm 1/60s - 20 s 1/30s - 20 s 1/4" 48 dB 49 dB 6.0 m x 6.0 m 10 mW/s @ 60C 0.22% of VPEAK-TO-PEAK 14.22 mm x 14.22 mm
Pb
Features
* * * * * * * * * * * * * * *
Note: The OV7950/OV7451 is available in a lead-free package.
Single chip 1/4" format video camera Composite video (NTSC) output High sensitivity Automatic exposure/gain with 16 zone control Horizontal and vertical windowing capability Auto white balance control Aperture/Gamma correction 50/60 Hz flicker cancellation External frame sync capability (Genlock) SPI/EEPROM used to control overlay and set other customer variables Two sets of dynamic overlay controls Master/slave compatible Serial Camera Control Bus (SCCB) control interface for register programming Low power consumption Extreme low dark current for high temperature applications Defective pixel correction
Figure 1 OV7950/OV7451 Pin Diagram (Top View)
DOGND HSYNC 19 18 17 16 15 14 13 VS ADGND ADVDD SCK ESO CS ESI FSIN RESET OVL2 OVLEn PWDN 12 11 10 9 8 7 43 MASTEN 44 MSDA 45 MSCL 46 SIO_D 47 SIO_C 48 SGND 1 SVDD 2 VREFH 3 VREFS 4 DEVDD 5 NVREF 6 VRLOW XCLK2 21 XCLK1 20 OGND OVDD DVDD 22 CVO 24 NC NC NC 27 NC 26
30 RES DOVDD PCLK NC NC NC 31 32 33 34 35 36
29
28
25
23
Ordering Information
Product OV07950-C10A (Color, NTSC) OV07451-C10A (B&W with microlens, NTSC) Package CLCC-48 CLCC-48
OV7950/OV7451
NC NC NC NC NC NC 37 38 39 40 41 42
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
1
OV7950/OV7451 Functional www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Description
This section describes the various functions of the OV7950/OV7451. Refer to Figure 2 for the functional block diagram of the OV7950/OV7451.
Figure 2 Functional Block Diagram
AMP Column Sample/Hold
ADC
DSP
Overlay
Video Encoder
DAC
+CVO
CS Row Select Image Array (656 x 492) Gain Control DSP Control Overlay Control SPI Interface SCK ESO ESI
CS0* Timing/Clock Generator Register Bank SCCB Interface CS1*
SIO_C
RESET
OVLEn
XCLK1
Video Standards
NTSC TV standards are implemented and available as output in the OV7950/OV7451 CAMERACHIPS. Note that the accuracy and stability of the crystal clock frequency is important to avoid unwanted color shift in the TV video system. OmniVision recommends using a 12.27 MHz crystal when utilizing the OV7950/OV7451 CAMERACHIP.
XCLK2
PWDN
Image Sensor Functions White Balance
The function of white balance in the OV7950/OV7451 CAMERACHIP is to adjust and calibrate the image device sensitivity on the primary (RGB) colors to match the color cast of the light source. The Auto White Balance (AWB) can be enabled or disabled by register control. If the AWB is enabled, the image sensors continuously perform white balancing.
Video Format
The OV7950/OV7451 CAMERACHIP supports Composite (CVBS) video format only. Composite signals are generated from the built-in TV encoder. The OV7451 only outputs the luminance signal.
Mirror and Vertical Flip
The OV7950/OV7451 provides horizontal mirror and vertical flip functions. These functions can be turned ON or OFF via register settings.
2
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
SIO_D
OVL2
FSIN
VS
Omni
ision
Functional Description
www..com
Multi-Chip Synchronize
The OV7950/OV7451 CAMERACHIP provides the multi-chip Synchronize function where one chip works as the master and all others as slave devices. The master chip provides the frame synchronize signal through pin VS (pin 18). All slave devices then accept the frame synchronize signal through pin FSIN. This mode allows all devices to synchronize together.
The receiver must pull down SIO_D during the acknowledgement bit time. During the write cycle, the OV7950/OV7451 device returns the acknowledgement and, during the read cycle, the master returns the acknowledgement, indicating to the slave that the read cycle can be terminated. Note that the restart feature is not supported here. Within each byte, the MSB is transferred first. The read/write control bit is the LSB of the first byte. Standard SCCB communications require only two pins, SIO_C and SIO_D. SIO_D is configured as an open drain for bidirectional purposes. A HIGH to LOW transition on the SIO_D while SIO_C is HIGH indicates a START condition. A LOW to HIGH transition on the SIO_D while SIO_C is HIGH indicates a STOP condition. Only a master can generate START/STOP conditions. Except for these two special conditions, the protocol that SIO_D remain stable during the HIGH period of the clock, SIO_C. Each bit is allowed to change state only when SIO_C is LOW (see Figure 3 and Figure 4). The OV7950/OV7451 SCCB interface supports multi-byte write and multi-byte read. The master must supply the sub-address in the write cycle, but not in the read cycle. Therefore, the OV7950/OV7451 takes the read sub-address from the previous write cycle. In multi-byte write or multi-byte read cycles, the sub-address automatically increments after the first data byte so that continuous locations can be accessed in one bus cycle. A multi-byte cycle overwrites its original sub-address; therefore, if a read cycle immediately follows a multi-byte cycle, a single byte write cycle that provides a new address must be inserted. The OV7950/OV7451 supports a single slave ID. The ID is preset to 60 for write and 61 for read. In the write cycle, the second byte in the SCCB is the sub-address for selecting the individual on-chip registers, and the third byte is the data associated with this register. Writing to the unimplemented sub-address is ignored. In the read cycle, the second byte is the data associated with the previously stored sub-address. Reading of an unimplemented sub-address returns unknown.
Chip Configuration
The OV7950/OV7451 CAMERACHIP has been designed for ease-of-use in many stand-alone applications. Some functions like serial interface slave address and NTSC selection can be set by connecting appropriate pins high (logic "1") or low (logic "0") through a 10 K resistor. The OV7950/OV7451 CAMERACHIP also has a serial master and slave interface for programmable access to all register functions.
Additional Picture Controls
The OV7950/OV7451 CAMERACHIP provides additional picture control functions to enhance image quality and chip performance. These functions are listed as follows: * AGC gain range control * Gamma correction * Brightness * Contrast * Full color bar test pattern
Serial Camera Control Bus (SCCB)
Many of the functions and configuration registers in the OV7950/OV7451 image sensors are available through the SCCB interface. The OV7950/OV7451 image sensor operates as a slave device that supports up to 400 kbps serial transfer rate using a 7-bit address/data transfer protocol.
SCCB Protocol Format
In SCCB operation (see Figure 5), the master must perform the following operations: * Generate the Start/Stop condition * Provide the serial clock on SIO_C * Place the 7-bit slave address (RW bit) and the 8-bit sub-address on SIO_D
Figure 3 Bit Transfer on the SCCB
SIO_D DATA STABLE SIO_C DATA CHANGE ALLOWED
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
3
OV7950/OV7451
www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
SCCB Master
Connect external SCCB slave-compatible storage device through the OV7950/OV7451 SCCB master interface so the OV7950/OV7451 can self load the configuration data from it. Data stored in the external storage device should be arranged as follows:
Address 0x00 0x01 0x02 0x03 . . .
Value Sub_add1 - first configuration register address Add1_value - first configuration register value Sub_add2 - second configuration register address Add2_value - second configuration register value . . .
When the sub_add = [FF] and add_value = [FF}, the SCCB master will stop operation.
Figure 4 Data Transfer on the SCCB
SIO_D
SLAVE ID
RW
SUB-ADDRESS
DATA
A
A
A
SIO_C S P
Figure 5 SCCB Protocol Format
FIRST BYTE S SLAVE (7-BIT) RW A SECOND BYTE SUB-ADDRESS (8-BIT) A THIRD BYTE DATA (8-BIT) A P
MSB START
LSB=0
ACK
ACK STOP
MASTER TRANSMIT, SLAVE RECEIVE (WRITE CYCLE)
FIRST BYTE S SLAVE (7-BIT) RW A SECOND BYTE SUB-ADDRESS (8-BIT) A P
MSB START
LSB=0
ACK STOP
MASTER TRANSMIT, SLAVE RECEIVE (DUMMY WRITE CYCLE)
FIRST BYTE S SLAVE (7-BIT) RW A SECOND BYTE DATA (8-BIT) A THIRD BYTE DATA (8-BIT) 1 P
MSB START
LSB=1
ACK
STOP NO ACK IN LAST BYTE
MASTER RECEIVE, SLAVE RECEIVE (READ CYCLE)
SLAVE ID - 1000000X X - RW BIT, 1: READ, 0: WRITE S - START CONDITION A - ACKNOWLEDGE BIT P - STOP CONDITION
- SLAVE TRANSMIT - MASTER TRANSMIT - MASTER INITIATE
4
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Functional Description
www..com
Overlay Control
The OV7950/OV7451 CAMERACHIP has an overlay capability where the user can store an overlay bit map image in an external storage device with an SPI interface. At power up, OV7950/OV7451 will start the SPI interface when the OVLEn pin (pin 8) is set high. [Bit7, Bit0] "10" in the first address indicates that there is no SPI slave device attached, causing the SPI interface to stop. Otherwise, the OV7950/OV7451 will check bit 6 of first byte for overwrite control. The user can define up to 15 bytes in the control register to overwrite the internal default value (further details defining this register is not available at this time). These 15 bytes only read one time after power up. If the first byte bit[7] is "1" and bit[0] is "0", OV7950/OV7451 will read the content in address 0x10 to 0x2B for the overlay setting.
Data formats are defined as follows: Address 0x10 Bit[7]: Bit[6]: Bit[7:6]: Bit[5:4]: Bit[3]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:6]: Bit[5:4]: Bit[3]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit[7:0]: Bit map 1 Description ON/OFF high bit ON/OFF low bit Opacity1[1:0] Resolution1[1:0] YUV1 all replaced Y1 U1 V1 V1 start[9:2] V1 end[9:2] H1 start[9:2] H1 end[9:2] V1 start[1:0], V1 end[1:0], H1 start[1:0], H1 end[1:0] MemLine1[7:0] (unit byte) Overlay set 2 start address low 8-bit Overlay set 2 start address high 8-bit Opacity2[1:0] Resolution2[1:0] YUV2 all replaced Y2 U2 V2 V2 start[9:2] V2 end[9:2] H2 start[9:2] H2 end[9:2] V2 start[1:0], V2 end[1:0], H2 start[1:0], H2 end[1:0] MemLine2[7:0] (unit byte)
0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x20
Figure 6
SPI Overlay Process Sequence
Power-up
0x21
Start SPI Read content in address 0x00~0x0F
0x22
N Stop SPI and Overlay
Do addresses 0x00[7] = 1 & 0x00[0] = 0 ? Y
0x23 0x24 0x25 0x26 0x27 0x28
Does address 0x00[6] = 1 ? Y Overwrite 15 bytes of internal registers with the content from addresses 0x01~0x0F
Read content in address 0x10~0x2B
Do addresses 0x10[7] = 1 & 0x10[6] = 0 ? Y
N
I2C Master Start Stop Overlay
0x29
Read I2C slave content one byte for address, one byte for data
Stop
0x2A 0x2B
N
Does pin OVL2 = 1 ?
Y
N Read current line overlay bit map 2 data
Read current line overlay bit map 1 data
Is there no ACK or does address = FF & data = FF ? Y Stop I2C Master
0x30 ~ 0xXX
Set2 start address Bit map 2 ~ 0xXX
Overlay process
Overlay process
Byte[10]
N
N
Field End?
Field End?
Overlay function can only be enabled when bit[7] = 1 and bit[6] = 0. There may be two sets of overlay bitmaps in one EPROM. Byte [11] ~ Byte [1A] are control bytes for first bitmap.
Y Reset address to 0x30
Y Reset address to the starting address of overlay bit map 2 (refer to addresses 0x21 and 0x20)
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
5
OV7950/OV7451
www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Byte [11]
Byte [1A]
00 2x2 01 3x3 10 4x4 11 5x5 Every time when a new line is started, it is necessary to go to a new address for memory reading. For example, if the user specifies 500 points per line, which is not an exact multiple of 8, they need at least 63 bytes (63 x 8 = 504) to save the information. So, they can only specify MemLine[7:0] to be a number equal or larger than [3F]. For example, If MemLine = [40]
Resolution =
When choosing 3x3 or 5x5, be aware that because YUV sampling format is 4:2:2, there may be strong color aliasing around the overlay edges. Opacity = 00 25% YUV all replaced: Enable: Y overlay = Y target x q% + Y original x (1-q%) U overlay = U target x q% + U original x (1-q%) V overlay = V target x q% + V original x (1-q%) Disable: Y overlay = Y target x q% + Y original x (1-q%) U overlay = U target V overlay = V target The q% is opacity. 01 50% 10 75% 11
Line 1 start address = [30], 100% reading sequence: Byte[20]bit7, bit6,...bit0, Byte[21]bit7, bit6...bit0, Byte[22]bit8, bit7...... ........... Byte[5E]bit8, bit7, bit6, bit5, bit4. END Line 2 start address = [70], Reading sequence: Byte[60]bit7, bit6,...bit0, Byte[61]bit7, bit6...bit0, Byte[62]bit8, bit7...... ........... Byte[9E]bit8, bit7, bit6, bit5, bit4. END So, in each line, there are 500 bits was read.
Byte [12]~[14] Byte [20], Byte [21]
Y, U, V specifies overlay color. In BW mode, only Y needed to be set. These two bytes indicate the 16-bit start address of the second bitmap.
Byte [15]~[19] Byte [22] ~ Byte [2B]
The user is allowed to specify vertical and horizontal dimensions of their overlay bitmap. If the desired figure is very small compared to the dimensions of the whole screen, they may save a lot of memory. These are control bytes for second bitmap (refer to description for Byte [11] ~ Byte [1A]).
6
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Pin Description
Pin Description www..com
Table 1
Pin Location 01 02 03 04 05 06
Pin Description
Name SVDD VREFH VREFS DEVDD NVREF VRLOW Pin Type Power Analog Analog Power Power Analog Default (V) 3.3 - - 0 0 - Function/Description Sensor array power supply Internal reference Internal reference Sensor array decoder power supply Internal reference Internal reference Power Down Mode ON/OFF Selection
07
PWDN
Input
0
0: 1:
OFF ON
Overlay ON/OFF selection 08 OVLEn Input 0 0: 1: OFF ON
Overlay bitmap file selection 09 OVL2 Input 0 0: 1: Select first bitmap Select second bitmap
Hard reset ON/OFF selection 10 RESET Input 0 0: 1: 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 FSIN ESI CS ESO SCK ADVDD ADGND VS HSYNC XCLK1 XCLK2 DVDD DOGND CVO OVDD Input Input Output I/O I/O Power Power Output Output Input Output Power Power Analog Power 0 0 - 0 0 3.3 0 0 0 - - 1.8 0 - 3.3 OFF ON
Frame synchronizing signal input SPI interface data input SPI interface chip select signal SPI interface data output SPI interface clock output ADC power supply ADC ground Frame synchronizing signal output Horizontal valid pixel reference signal output Crystal input Crystal output Digital core power supply Digital I/O interface ground Composite video signal output DAC power supply Proprietary to OmniVision Technologies 7
Version 2.5, February 28, 2006
OV7950/OV7451
Table 1 Pin www..com
Pin Location 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Description
Pin Type - - - - Analog Analog Power Output - - - - - - - - - Input I/O O I/O Input Power Default (V) - - - - - - 3.3 - - - - - - - - - - - - - - - 0 No connection No connection No connection No connection DAC ground Internal reference adjustment pin (connect to ground using a 200 resistor) Digital I/O interface power supply Pixel clock output No connection No connection No connection No connection No connection No connection No connection No connection No connection Master interface enable Serial master interface data I/O Serial master interface clock output Serial slave interface data I/O Serial slave interface clock input Sensor array ground Function/Description
Name NC NC NC NC OGND RES DOVDD PCLK NC NC NC NC NC NC NC NC NC MASTEN MSDA MSCL SIO_D SIO_C SGND
8
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Electrical Characteristics
Electrical Characteristics www..com
Table 2 Operating Conditions
Parameter Operating temperature Storage temperaturea
a.
Min -40C -40C
Max +85C +125C
Exceeding the stresses listed may permanently damage the device. This is a stress rating only and functional operation of the sensor at these and any other condition above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions for any extended period may affect reliability.
Table 3
Symbol Supply VDD1 VDD2 IDD
DC Characteristics (-20C < TA < 85C, Voltages Referenced to GND)
Parameter Min Typ Max Unit
Supply voltage (SVDD, DOVDD, EVDD) Supply voltage (DVDD) Supply current
3.15 1.70 -
3.3 1.8 60
3.45 1.90 -
V V mA
Digital Inputs VIL VIH CIN Input voltage LOW Input voltage HIGH Input capacitor 0.8 x DOVDD 10 0.2 x DOVDD V V pF
Digital Outputs (standard loading 25 pF, 1.2 K to 3V VOH VOL Serial Input VIL VIH SIO_C and SIO_D SIO_C and SIO_D -0.5 2.5 0 3.3 1 VDOVDD + 0.5 V V Output voltage HIGH Output voltage LOW 2 0.6 V V
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
9
OV7950/OV7451
Table 4 AC www..com
Symbol
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Characteristics (TA = 25C, VDD = 5V)
Parameter Min Typ Max Unit
Clock Input / Crystal Oscillator fOSC Resonator frequency (NTSC) Load capacitor Parallel resistance Rise/fall time for external clock input Duty cycle for external clock input CVO Analog Video Output Parameters VTO_P VTO_B VVSYNC VSYNCLEVEL IVTO I/O Pin ISOURCE ISINK Output pin source current (Output = 1.5V) Output pin sink current (Output = 3V) 8 8 10 10 12 12 mA mA Video peak signal level Video black signal level Video sync pulse amplitude Sync level Video output drive current 0.969 0.339 0.291 0.017 - 1.020 0.357 0.306 0.022 1.071 0.375 0.321 0.027 30 V V V V mA - 40 - 12.27 33 1 5 50 - 60 - MHz pF M ns %
Miscellaneous Timing tSYNC tPU External FSIN cycle time Chip power-up time - - 2 - - 100 field s
10
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Timing Specifications
Timing Specifications www..com
NTSC Timing
Figure 7 NTSC Standard Video Timing Diagram
HSYNC HSYNC / 2
HCOUNT / 2 HCOUNT / 2
HCOUNT / 2 HCOUNT / 2
ANALOG FIELD 1
520
521
522
523
524
525 START OF VSYNC
1
2
3
4
5
6
7
13
ANALOG FIELD 2
258
259
260
261
262
263
264
265
266
267
268
269
275
276
Figure 8 NTSC Composite Video Signal
MAGENTA
YELLOW
GREEN
CYAN
1.13 V
BLACK
WHITE LEVEL BLACK LEVEL BLANK LEVEL SYNC LEVEL
WHITE
100 IRE 3.58 MHZ COLOR BURST (9 CYCLES) 0.449 V 20 IRE 0.357 V 0.306 V 20 IRE 0.163 V 40 IRE 0.022 V 7.5 IRE
Version 2.5, February 28, 2006
BLUE
RED
Proprietary to OmniVision Technologies
11
OV7950/OV7451
Overlay Timing www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Figure 9 Vertical Timing Diagram
PWUP VS HSYNC CS
... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ...
... ... ... ... ...
... ...
SCK
... ...
...
Read 16 System Control Bytes FromEPROM [0000] ~ [000F]
Available when power up.
Read 28 Overlay Control Bytes FromEPROM [0010] ~ [002B]
Only available when EPROM check successful.
Part II: Read Overlay Bitmap From EPROM [0030] ~ [XXXX]
Available in every field, If overlay function is ON.
Part I: Read Control Bytes
Only in the first Field, after Chip Power up
In Pa rt I, SCK freq. is always 1/5 pixel clock freq; In Pa rt II, SCK freq. can be 1/2, 1/3, 1/4 or 1/5 pixel clock freq. according to overlay resolution (2x2, 3x3, 4x4 or 5x5).
Figure 10 Horizontal Timing Diagram
HSYNC Overlay HREF CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
175 176 177 178 179
312 pixels,
156 overlay bits
SCK
INSTRUCTION: READ
... ...
... ...
BYTE ADDRESS = [0058]
15 14 13 12 11 10 2 1 0
ESO
ESI
BYTE [0058] HIGH IMPEDANCE
7 6 5 4 3 2 1 07 6
BYTE [0059]
5 4 3 2 1 0
BYTE [006B]
... ...
HIGH IMPEDANCE
07 6 5 4
If overlay resolution is 2x2, overlay horizontal start = [60] overlay horizontal end = [198] MEMLN = [14] So, overlay HREF includes 312 pixels. In each line, it need to read 156 bits from overlay bitmap in EPROM. In overlay line1 or line2, read EPROM BYTE [0030] ~ [0043]; In overlay line3 or line4, read EPROM BYTE [0044] ~ [0057]; Figure 11 shows horizontal timing of overlay line5 or line6.
12
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Timing Specifications
Interface Timing www..com
Figure 11 SCCB Timing Diagram
tF tLOW SIO_C tSU:STA SIO_D IN t BUF tAA SIO_D OUT t DH t HD:STA t HD:DAT t SU:DAT tSU:STO t HIGH tR
Table 5
Symbol fSIO_C tLOW tHIGH tAA tBUF tHD:STA tSU:STA tHD:DAT tSU:DAT tSU:STO tR, tF tDH
SCCB Timing Specifications
Parameter Clock Frequency Clock Low Period Clock High Period SIO_C low to Data Out valid Bus free time before new START START condition Hold time START condition Setup time Data-in Hold time Data-in Setup time STOP condition Setup time SCCB Rise/Fall times Data-out Hold time 50 1.3 600 100 1.3 600 600 0 100 600 300 900 Min Typ Max 400 Unit KHz s ns ns s ns ns s ns ns ns ns
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
13
OV7950/OV7451
Figure 12 SPI www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Timing Diagram
tCS
CS
tCSS
SCK
tCSH tWH tWL
tSU
ESO
VALID IN
tH
tV
ESI
HI-Z
tHO
tDIS
HI-Z
Table 6
Symbol tWH tWL tCS tCSS tCSH tSU tH tV tHO tDIS
SPI Timing Specifications
Parameter SCK High Time SCK Low Time CS High Time CS Setup Time CS Hold Time Data In Setup Time Data In Hold Time Output Valid Output Hold Time Output Disable Time 0 250 Min 133 133 250 250 250 50 50 133 Typ Max Unit ns ns ns ns ns ns ns ns ns ns
14
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Timing Specifications
OV7950 Light www..com
Response
Figure 13 OV7950 Light Response
spectrum_7950
5.00E+10 4.50E+10 4.00E+10 3.50E+10 Output(mv/w.s) 3.00E+10 2.50E+10 2.00E+10 1.50E+10 1.00E+10 5.00E+09 0.00E+00 395 495 595 695 795 895 995 1095 R G B
w av elength
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
15
OV7950/OV7451 Register Set www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Table 7 provides a list and description of the Device Control registers contained in the OV7950/OV7451. The device slave addresses are 60 for write and 61 for read.
Table 7
Address (Hex)
Device Control Register List
Register Name Default (Hex) R/W AGC Gain Control Gain setting * Range: 1x - 32x Gain = (Bit[7]+1) x (Bit[6]+1) x (Bit[5]+1) x (Bit[4]+1) x (1+Bit[3:0]/16) Note: This register is updated automatically when AGC is enabled. The user can adjust the value through the serial interface if AGC is disabled. Blue Gain Control Red Gain Control Green Gain Control AEC/AGC Control Bit[7:0]: Description
00
GAIN
00
RW
01 02 03
BLUE RED GREEN
80 80 80
RW RW RW
04
AECL
88
RW
Bit[7:3]: Bit[2:1]: Bit[0]:
Reserved AGC Gain Control - high 2 bits Exposure control LSB
05 06 07
BAVG GAVG RAVG
00 00 00
RW RW RW
B Channel Average G Channel Average R Channel Average Common Control 1 Bit[7]: Mirror function 0: Normal image 1: Mirror image Vertical flip function 0: Normal image 1: Vertically flip image Reserved VS pin output selection 0: Output signal depends on COM7[1] (0x15) 1: Output Odd field indicator Gamma function ON/OFF 0: Gamma OFF 1: Gamma ON Reserved
Bit[6]:
08
COM1
10
RW
Bit[5]: Bit[4]:
Bit[3]:
Bit[2:0]: 09 0A 0B 0C-0F RSVD PIDH PIDL RSVD XX 79 50 XX - R R - Reserved
Product ID Number MSB (Read only) Product ID Number LSB (Read only) Reserved
16
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Register Set
Table 7 Device www..com
Address (Hex) 10 11
Control Register List (Continued)
Default (Hex) 82 XX R/W RW - Description Automatic Exposure Control - AEC[8:1] (LSB in AECL[0] (0x04) and MSB in AECH[6:0] (0x39)) Reserved Common Control 4 Bit[7]: SRST 0: No change 1: Initiates system reset and resets all registers to factory default values after which the device resumes normal operation Reserved
Register Name AEC RSVD
12
COM4
50
RW
Bit[6:0]:
AEC, AGC, and AWB Auto/Manual Control Bit[7]: AEC speed selection 0: Normal 1: Faster AEC correction Reserved Banding filter ON/OFF selection 0: OFF 1: ON Reserved Small exposure ON/OFF selection 0: OFF (minimum exposure is 1 Tv line period (65 s)) 1: ON (minimum exposure is 20 s) AGC auto/manual control selection 0: Manual 1: Auto AWB auto/manual control selection 0: Manual 1: Auto Exposure control 0: Manual 1: Auto
Bit[6]: Bit[5]:
Bit[4]: Bit[3]: 13 COM5 8F RW Bit[2]:
Bit[1]:
Bit[0]:
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
17
OV7950/OV7451
Table 7 Device www..com
Address (Hex)
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM Control Register List (Continued)
Default (Hex) R/W Common Control 6 Bit[7:5]: AGC max gain ceiling 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101-111: Not allowed Reserved Digital gain ceiling 00: 1x 01: 2x 10: 4x 11: Not allowed Reserved Exposure freeze ON/OFF 0: OFF 1: ON Description
Omni
ision
Register Name
14
COM6
80
RW
Bit[4]: Bit[3:2]:
Bit[1]: Bit[0]:
Common Control 7 Bit[7:2]: Bit[1]: Reserved VSYNC output selection 0: Field VSYNC 1: Frame VSYNC Reserved
15
COM7
00
RW
Bit[0]:
Common Control 8 Bit[7]: AEC/AGC algorithm selection 0: Average-based AEC/AGC control 1: Histogram-based AEC/AGC control Auto/Manual digital gain select 0: Auto digital gain 1: Manual digital gain Manual set digital gain [1:0] Reserved
16
COM8
40
RW
Bit[6]:
Bit[5:4]: Bit[3:0]: 17-1A 1B 1C 1D 1E-20 RSVD PSHFT MIDH MIDL RSVD XX 6A 7F A2 XX - RW R R - Reserved
Left Pixel Shift - 1 bit equals 2 pixel shift Manufacturer ID Byte - High Manufacturer ID Byte - Low Reserved (Read only = 0x7F) (Read only = 0xA2)
18
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Register Set
Table 7 Device www..com
Address (Hex)
Control Register List (Continued)
Default (Hex) R/W Common Control 9 Bit[7]: Bit[6]: Reserved VSYNC output pattern control 0: VSYNC can start at line start or half line 1: VSYNC can only start at line start VSYNC output only in field one VSYNC output only in field two Reserved Description
Register Name
21
COM9
00
RW Bit[5]: Bit[4]: Bit[3:0]:
22-23 24 25 26 27-2E 2F 30-32 33 34-38
RSVD AECW AECB VWB RSVD YAVG RSVD VSFT RSVD
XX 78 68 D4 XX 00 XX 00 XX
- RW RW RW - RW - RW -
Reserved Luminance Signal High Range for AEC/AGC operation Luminance Signal Low Range for AEC/AGC operation Fast Mode Large Step Luminance Range Threshold Reserved Luminance Average Value Reserved Vertical Window Shift Reserved Automatic Exposure Control MSBs
39
AECH
82
RW
Bit[7]: Bit[6:0]: Reserved Monitor Bit[7:4]:
Reserved Automatic exposure control MSBs
3A-65
RSVD
XX
-
66
MNTR
00
RW Bit[3:0]:
Register monitor control (refer to descriptions of registers COM22 (0xED), COM23 (0xEE), COM24 (0xEF) and COM25 (0xF0) Reserved
67-7A
RSVD
XX
-
Reserved Gamma Curve Highest Segment Slop Should be calculated as follows: SLOP[7:0] = (FF - GAM15[7:0] + 1) x 40/30 Note: Use hex numbers for calculation
7B
SLOP
24
RW
7C 7D 7E 7F 80 81
GAM1 GAM2 GAM3 GAM4 GAM5 GAM6
0F 1F 36 54 5F 6A
RW RW RW RW RW RW
Gamma Curve - 1st segment input end point 0x010 output value Gamma Curve - 2nd segment input end point 0x020 output value Gamma Curve - 3rd segment input end point 0x040 output value Gamma Curve - 4th segment input end point 0x080 output value Gamma Curve - 5th segment input end point 0x0A0 output value Gamma Curve - 6th segment input end point 0x0C0 output value
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
19
OV7950/OV7451
Table 7 Device www..com
Address (Hex) 82 83 84 85 86 87 88 89 8A 8B-9A 9B 9C 9D 9E 9F A0
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM Control Register List (Continued)
Default (Hex) 74 7C 84 8C 9A A7 BF D3 E5 XX 40 34 0C 17 29 40 R/W RW RW RW RW RW RW RW RW RW - RW RW RW RW RW RW Description
Omni
ision
Register Name GAM7 GAM8 GAM9 GAM10 GAM11 GAM12 GAM13 GAM14 GAM15 RSVD MTX1 MTX2 MTX3 MTX4 MTX5 MTX6
Gamma Curve - 7th segment input end point 0x0E0 output value Gamma Curve - 8th segment input end point 0x100 output value Gamma Curve - 9th segment input end point 0x120 output value Gamma Curve - 10th segment input end point 0x140 output value Gamma Curve - 11th segment input end point 0x180 output value Gamma Curve - 12th segment input end point 0x1C0 output value Gamma Curve - 13th segment input end point 0x240 output value Gamma Curve - 14th segment input end point 0x2C0 output value Gamma Curve - 15th segment input end point 0x340 output value Reserved Color Matrix Parameter M1 Color Matrix Parameter M2 Color Matrix Parameter M3 Color Matrix Parameter M4 Color Matrix Parameter M5 Color Matrix Parameter M6 Color Matrix Control Bit[7]: Bit[6]: Bit[5]: Bit[4]: Bit[3]: Bit[2]: Bit[1]: Bit[0]: Double matrix - double M1 to M6 Reserved Sign bit of M6 Sign bit of M5 Sign bit of M4 Sign bit of M3 Sign bit of M2 Sign bit of M1
A1
MTX7
1E
RW
A2 A3 A4-BE BF C0 C1 C2 C3 C4 20
BRT CNTR RSVD BPTH1 BPTH2 WPTH1 WPTH2 BPCNT1 BPCNT2
00 40 XX 90 40 A0 D0 CC F0
RW RW - RW RW RW RW RW RW
Brightness Control * Range [00] to [FF} Contrast Control Reserved Black Pixel Threshold Level 1 Black Pixel Threshold Level 2 White Pixel Threshold Level 1 White Pixel Threshold Level 2 Black Pixel Count Number 1 Black Pixel Count Number 2 Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
Omni
ision
Register Set
Table 7 Device www..com
Address (Hex) C5 C6 C7-D0
Control Register List (Continued)
Default (Hex) 64 80 XX R/W RW RW - White Pixel Count Number 1 White Pixel Count Number 2 Reserved Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: Reserved Overlay Data Shift Select Reserved Register Monitor when MNTR[7:4] are: 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: SPI input com1 SPI input com2 SPI input com3 SPI input com4 SPI input com5 SPI input com6 SPI input com7 SPI input com8 SPI input com9 SPI input com10 SPI input com11 SPI input com12 SPI input com13 SPI input com14 SPI input com15 SPI input com16 Zone 4 Zone 3 Zone 2 Zone 1 Zone 8 Zone 7 Zone 6 Zone 5 Zone 12 Zone 11 Zone 10 Zone 8 Zone 16 Zone 15 Zone 14 Zone 13 16-Zone Y average select In each zone, the two bits mean: 00: Not selected 01: Weight x1 10: Weight x2 11: Weight x4 H Start V Start 1 2 3 4 Description
Register Name WPCNT1 WPCNT2 RSVD
D1
ZONE1
FF
RW
D2
ZONE2
FF
RW
D3
ZONE3
FF
RW
5
6
7
8
9 D4 ZONE4 FF RW
10
11
12
13
14
15
16
D5-EA EB EC
RSVD COM21 RSVD
XX 00 XX
- RW -
ED
COM22
-
R
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
21
OV7950/OV7451
Table 7 Device www..com
Address (Hex)
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM Control Register List (Continued)
Default (Hex) R/W Description Register Monitor when MNTR[7:4] are: 0000: Bit[7:6]: Overlay control register Overlay function ON/OFF select 0x: Overlay function OFF 10: Overlay function ON 11: Overlay function OFF Overlay bitmap 1 control register Overlay opacity 00: 25% overlay opacity 01: 50% overlay opacity 10: 75% overlay opacity 11: 100% overlay opacity Overlay resolution 00: 2x2 01: 3x3 10: 4x4 11: 5x5 Y overlay target 1 U overlay target 1 V overlay target 1 Overlay vertical window 1 start point MSBs Overlay vertical window 1 stop point MSBs Overlay horizontal window 1 start point MSBs Overlay horizontal window 1 stop point MSBs Reserved Overlay vertical window 1 start point LSBs Overlay vertical window 1 stop point LSBs Overlay horizontal window 1 start point LSBs Overlay horizontal window 1 stop point LSBs Memory length for one line Overlay bit map 2 start address LSBs Overlay bit map 2 start address MSBs Overlay bitmap 2 control register Y overlay target 2 U overlay target 2
Omni
ision
Register Name
0001: Bit[7:6]:
Bit[7:6]:
EE
COM23
-
R
0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: 1010: 1011: 1100: 1101: 1110: 1111:
Register Monitor when MNTR[7:4] are: 0000: 0001: 0010: 0011: 0100: 0101: Bit[7:6]: Bit[5:4]: Bit[3:2]: Bit[1:0]: 0110: V overlay target 2 Overlay vertical window 2 start point MSBs Overlay vertical window 2 stop point MSBs Overlay horizontal window 2 start point MSBs Overlay horizontal window 2 stop point MSBs Reserved Overlay vertical window 2 start point LSBs Overlay vertical window 2 stop point LSBs Overlay horizontal window 2 start point LSBs Overlay horizontal window 2 stop point LSBs Memory length 2 for one line
EF
COM24
-
R
22
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Register Set
Table 7 Device www..com
Address (Hex)
Control Register List (Continued)
Default (Hex) R/W Description Register Monitor when MNTR[7:4] are: 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: Reserved Y average zone 1 Y average zone 2 Y average zone 3 Y average zone 4 Y average zone 5 Y average zone 6 Y average zone 7 Y average zone 8 Y average zone 9 Y average zone 10 Y average zone 11 Y average zone 12 Y average zone 13 Y average zone 14 Y average zone 15 Y average zone 16
Register Name
F0
COM25
-
R
F1-F2
RSVD
XX
-
NOTE: All other registers are factory-reserved. Please contact OmniVision Technologies for reference register settings.
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
23
OV7950/OV7451
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Package Specifications www..com
The OV7950/OV7451 uses a 48-pin ceramic package (CLCC). Refer to Figure 14 and Table 8 for CLCC information and Figure 15 for the sensor array center.
Figure 14 OV7950/OV7451 Package Specifications
.088 - .011 .065 - .007 .030 - .002 .015 - .002 .020 - .002 30
.560 SQ + .012 / - .005 .430 SQ - .005 42 43 43 .032 MIN 48 1 48 1 Pin 1 Index 6 6 7 7 18 18 19 19 42 .350 SQ - .005 31 30 31
.440 - .005 .040 - .003 31 30 .022 - .004 .001 to .005 TYP 42
.06 +.010 -.005 .040 TYP 43
.488 - .004 Glass Image Plane
0.029 - .001 Die .037 - .007
48 1
.012 TYP REF R .0075 (4 CORNERS)
19
.020 TYP 18 R .0075 (48 PLCS) 7
6
.085 TYP
Table 8
OV7950/OV7451 Package Dimensions
Dimensions Millimeters (mm) 14.22 + 0.30 / -0.13 SQ 2.23 + 0.28 0.51 + 0.05 8.89 + 0.13 SQ 1.14 + 0.13 0.51 x 2.16 0.51 x 1.02 1.02 + 0.08 1.524 + 0.25 / -0.13 11.18 + 0.13 12.40 + 0.10 SQ / 13.00 + 0.10 SQ 0.55 + 0.05 0.733 + 0.015 0.95 + 0.18 1.65 + 0.18 Inches (in.) .560 + .012 / - .005 SQ .088 + .011 .020 + .002 .350 + .005 SQ .045 + .005 .020 x .085 .020 x .040 .040 + .003 .06 + .010 / - .005 .440 + .005 .488 + .004 SQ / .512 + .004 SQ .022 + .002 .029 + .001 .037 + .007 .065 + .007
Package Size Package Height Substrate Base Height Cavity Size Castellation Height Pin #1 Pad Size Pad Size Pad Pitch Package Edge to First Lead Center End-to-End Pad Center-Center Glass Size Glass Height Die Thickness Top of Glass to Image Plane Substrate Height
24
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Package Specifications
Sensor Array www..com
Center
Figure 15 OV7950/OV7451 Sensor Array Center
A rray C enter (-127.5 m, 812.6 m)
1
S c an Origin
4080 m 3102 m
S ens or A rray P ac kage C enter (0,0) Die S c an E nd P ac kage
TOP V IE W
NOT E S : 1. T his drawing is not to s cale and is for reference only. 2. As mos t optical as s emblies invert and mirror the image, the chip is typically mounted with pin one oriented down on the P C B .
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
25
OV7950/OV7451
IR Reflow Ramp www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
Rate Requirements
OV7950/OV7451 Lead-Free Packaged Devices
Figure 16 IR Reflow Ramp Rate Requirements
300.0 280.0 260.0 240.0 220.0 200.0 Temperature ( C ) 180.0 160.0 140.0 120.0 100.0 80.0 60.0 40.0 20.0 0.0 -22 -2 0.0 18 38 0.6 58 78 1.1 98 118 1.6 138 158 2.2 178 198 2.8 218 238 3.3 258 278 3.9 298 318 338 358 369 Z1 Z2 Z3 Z4 Z5 Z6 Z7 end
Time (sec) -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9
Time (min.)
Table 9
Reflow Conditions
Condition Exposure Less than 3C per second Between 330 - 600 seconds At least 210 seconds At least 30 seconds (30 ~ 120 seconds) 245C Less than 6C per second No greater than 390 seconds
Average Ramp-up Rate (30C to 217C) > 100C > 150C > 217C Peak Temperature Cool-down Rate (Peak to 50C) Time from 30C to 245C
26
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
Omni
ision
Package Specifications
www..com
Note:
*
All information shown herein is current as of the revision and publication date. Please refer to the OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). Reproduction of information in OmniVision product documentation and specifications is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. In such cases, OmniVision is not responsible or liable for any information reproduced. This document is provided with no warranties whatsoever, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification or sample. Furthermore, OmniVision Technologies Inc. disclaims all liability, including liability for infringement of any proprietary rights, relating to use of information in this document. No license, expressed or implied, by estoppels or otherwise, to any intellectual property rights is granted herein. `OmniVision' and `OmniPixel' are trademarks of OmniVision Technologies, Inc. All other trade, product or service names referenced in this release may be trademarks or registered trademarks of their respective holders. Third-party brands, names, and trademarks are the property of their respective owners.
*
*
*
*
For further information, please feel free to contact OmniVision at info@ovt.com.
OmniVision Technologies, Inc. 1341 Orleans Drive Sunnyvale, CA USA (408) 542-3000
Version 2.5, February 28, 2006
Proprietary to OmniVision Technologies
27
OV7950/OV7451
www..com
CMOS Analog NTSC (OmniPixel(R)) CAMERACHIPTM
Omni
ision
28
Proprietary to OmniVision Technologies
Version 2.5, February 28, 2006
www..com
Omni
Document Title:
ision
TM
REVISION CHANGE LIST
OV7950/OV7451 Datasheet (non-auto apps) Version: 2.3
DESCRIPTION OF CHANGES
Initial Release (created using OV7950/OV7451 ver 1.3 (for auto apps) with the following changes): * * * * * Deleted "for Automotive Applications" from the title. Under Ordering Information, changed the part number from OV07950-Q10V and OV07451-Q10V to OV07950-C10A and OV07451-C10A. Changed bullet list under Applications on page 1. Changed Figure 1 to show pinout diagram for CLCC package. Under Package Specifications on page 24, changed Figure 14 and Table 8 to show CLCC package drawing and CLCC package dimensions table.
www..com
Omni
Document Title:
ision
TM
REVISION CHANGE LIST
OV7950/OV7451 Datasheet (non-auto apps) Version: 2.4
DESCRIPTION OF CHANGES
The following changes were made to version 2.3: * * Added Figure 13 (OV7950 Light Response graph) on page 15 Under Features on page 1, changed second bullet from "Composite video (NTSC) differential output drive" to "Composite video (NTSC) output"
www..com
Omni
Document Title:
ision
TM
REVISION CHANGE LIST
OV7950/OV7451 Datasheet (non-auto apps) Version: 2.5
DESCRIPTION OF CHANGES
The following changes were made to version 2.4: * * * * * * * * * * * Under Key Specifications on page 1, changed Power Consumption from "TBD" to "200 mW" Under Key Specifications on page 1, changed S/N Ratio from "TBD" to "48 dB" Under Key Specifications on page 1, changed Dynamic Range from "TBD" to "49 dB" Under Key Specifications on page 1, changed Dark Current from "TBD" to "10 mW/s @ 60C" Under Key Specifications on page 1, changed Fixed Pattern Noise from "TBD" to "0.22% of VPEAK-TO-PEAK" In Table 1 on page 7, changed Default value for pin 02 from "TBD" to "-" In Table 1 on page 7, changed Default value for pin 03 from "TBD" to "-" In Table 1 on page 7, changed Default value for pin 06 from "TBD" to "-" In Table 2 on page 9, changed Min and Max for Operating temperature from "TBD" and "TBD" to "-40C" and "+85C", respectively. In Table 2 on page 9, deleted table row for Storage Humidity. In Table 3 on page 9, added the table footnote: "Exceeding the stresses listed may permanently damage the device. This is a stress rating only and functional operation of the sensor at these and any other condition above those indicated in this specification is not implied. Exposure to absolute maximum rating conditions for any extended period may affect reliability." In Table 3 on page 9, changed Typ for Supply current (IDD) from "TBD" to "60" In Figure 8 on page 11, changed callout from "1.020 V" to "1.13V"
* *

▲Up To Search▲

Price & Availability of OV7451

	To Download OV7451 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .